Non-volatile memory (NVM) arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array. NVM cells generally comprise transistors with programmable threshold voltages. For example, one type of non-volatile cell is a nitride, read only memory (NROM) cell, described in U.S. Pat. No. 6,011,725, the disclosure of which is incorporated herein by reference.
One preferred procedure for programming bits, e.g., in NROM cells, is by the application of programming pulses to word lines and bit lines so as to increase the threshold voltage of the bits to be programmed. After application of one or more sets of programming pulses, the threshold voltages of the bits that are to be programmed may be verified to check if the threshold voltages have been increased to a target programmed state. Any bit that fails the program verify operation should preferably undergo one or more extra programming pulses. The sequence of application of programming pulses followed by verification may then continue until all the bits that should be programmed have reached the target programmed state.
Read and write operations are typically carried out with voltages that are regulated above a positive voltage supply Vdd. The circuitry that supplies and controls the programming and verification voltages generally comprises a high voltage regulator or high voltage pump (the terms being used herein interchangeably). A typical EPROM system is shown in FIG. 1. A charge pump 5 pumps a voltage supply Vpp to a voltage amplifier (also called a differential stage) 6. Differential stage 6 receives an input voltage REF at one of its inputs (the positive input in the illustration). The output of differential stage 6 may be connected via a node n1 to an inverter 7. The inverter 7 may be connected to a negative and/or ground drive, and through a capacitor 8 back to the second input (the negative input in the illustration) of differential stage 6 as its feedback FB. An X-decoder (XDEC) 9 may also be connected to inverter 7. The circuitry of FIG. 1 may drive the voltages for word lines (WL) of an array, which also includes bit lines (BL).
For example, it may be necessary to drive the word line to which the gate of a memory transistor (or cell) is connected to different voltage levels in order to read, program or erase it The load to be driven includes the word line, X-decoder (XDEC) and associated N-wells. This may be a very large capacitive load for a VLSI (very large scale integrated) circuit, ranging in value from 100 pF to several nF. During program (PGM) mode, the word line and associated voltages may be typically at a programming voltage (Vpgm) in the range of 8 to 11V, whereas in read (RD) or verify (VERF) modes, the word line may be typically at a read voltage (Vrd) in the range of 3 to 6V. The regulator may have to drive the voltage transition between the different modes in a short time span (0.1-2 μs).
Conventional voltage regulators use the well-known Miller architecture, a typical example of which is illustrated in FIG. 2.
An NMOS (n-channel metal oxide semiconductor) transistor XA1A has its gate connected to an input BGREF, its drain connected to a node N1, and its source connected to a node N2. A PMOS (p-channel metal oxide semiconductor) transistor XA2A has its gate connected to a node MG, its drain connected via node N1 to the drain of NMOS transistor XA1A, and its source connected to some reference voltage. Another PMOS transistor XA2B has its gate connected via node MG to the gate of PMOS transistor XA2A, its drain connected via nodes N4 and MG to its gate, and its source connected to some reference voltage.
An NMOS transistor XA3A has its drain connected via node N2 to the source of NMOS transistor XA1A, its gate connected to the gate of an NMOS transistor XA3B, and its source may be grounded. NMOS transistor XA3B has its gate and drain connected to a node N3, and its source may be grounded. Node N3 is connected to a current source I1.
An NMOS transistor XA1B has its drain connected via node N4 to the drain of PMOS transistor XA2B, its gate connected to a node N5, and its source connected via node N2 to the drain of NMOS transistor XA3A.
Another PMOS transistor XA4 has its gate connected to a node N6, its drain connected to a node N7, and its source connected to some reference voltage. A resistor R0 may be connected between nodes N5 and N7, and another resistor R1 may be connected between node N5 and ground. Resistors R0 and R1 form a resistive divider. A capacitance load Cload may be connected to node N7 via a node N8, and may be grounded. The output node is designated as OP.
The circuitry of transistors XA1A, XA2A, XA3A, XA3B, XA1B and XA2B forms the first stage of the Miller architecture, and the circuitry of transistor XA4 forms the second stage of the Miller architecture, with feedback FB from node N5 to the gate of transistor XA1B. A Miller compensating capacitor CM is connected between nodes N6 and N7. PG is the input to the second stage (gate of transistor XA4). The dominant (primary) pole is at node N6 and the secondary pole is at node N7.
The Miller architecture may be problematic in many EPROM applications, wherein the capacitance load Cload is large. This is because the non-dominant pole, referred to as p2 (node N7), is associated with the output node (OP) (via node N8). Using an open loop analysis (see, for example, P. E. Allen and D. R. Holberg in “CMOS Analog Circuit Design” (Oxford University Press, 2002), pp. 259), the condition for stability is that p2 be greater than or equal to 3 times the unity gain bandwidth (GBW):p2>3×GBW  (Eq. 1)
wherein p2=gm2/Cload (Eq. 2) and GBW=gm1/Cm (Eq. 3), assuming a unity gain buffer, i.e., FB=OP, and wherein the transconductances of the first and second stages are gm1 and gm2 respectively.
The stability condition implies that the non-dominant pole, which in this case includes a very large output capacitor, will ultimately set the bandwidth.
There are a large variety of Class AB drivers reported in the literature. These include circuits that increase the tail current when a signal is present (see, for example, R. Klinke, B. J. Hosticka, and H. Pfleiderer, IEEE J. Solid State Circuits 24, pp. 744-746 (1989)). Others use a transistor biased near Vt and increase the Vgs when necessary (see, for example,) B. Fotouhi, IEEE J. Solid State Circuits 38, pp. 226-236 (2003)). Class AB operation can also be achieved using back-to-back source followers (see, for example, J. S. Shor, Y. Sofer, Y. Polansky, and E. Maayan, in ISCAS 2002: International Symposium on Circuits and Systems, paper # WA2.04.01, May 26-29, 2002, Phoenix, Ariz.). The Class AB architectures typically use either a Miller configuration, or are single stage regulators.